A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process

Applications like ultra-wideband radio, optical communication require sampling rates of at least 500 MS/s with low resolution. The potential energy savings of successive approximation based time-interleaved A-D conversion architecture overrides traditional flash architecture. This paper presents a 6-bit 800 MS/s ADC in 65 nm STMicroelectronics standard CMOS process. The ADC uses 8-channel time interleaved SAR topology and achieves 36 dB SNR and 43 dB SFDR with 13.5 mW power consumption from 1.2 V supply. The resulting FOM is 0.3251 pJ/step. The timing mismatch among the channels is reduced by clock-edge reassignment technique. The high speed specification of the system requires the design of low offset comparator. Power consumption and jitter are reduced by using shift register based phase generator.