DocumentCode :
3322035
Title :
Analysis of parallel processor architectures for the solution of the Black-Scholes PDE
Author :
Laszlo, Endre ; Nagy, Zoltan ; Giles, Michael B. ; Reguly, Istvan ; Appleyard, Jeremy ; Szolgay, Peter
Author_Institution :
Pazmany Peter Catholic Univ., Budapest, Hungary
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
1977
Lastpage :
1980
Abstract :
Common parallel computer microarchitectures offer a wide variety of solutions to implement numerical algorithms. The efficiency of different algorithms applied to the same problem vary with the underlying architecture which can be a multi-core CPU, many-core GPU, Intel´s MIC (Many Integrated Core) or FPGA architecture. Significant differences between these architectures exist in the ISA (Instruction Set Architecture) and the way the compute flow is executed. The way parallelism is expressed changes with the ISA, thread management and customization available on the device. These differences pose restrictions to the implementable algorithms. The aim of the work is to analyze the efficiency of the algorithms through the architectural differences. The problem at hand is the one-factor Black-Scholes option pricing equation which is a parabolic PDE solved with explicit and implicit time-marching algorithms. In the implicit solution a scalar tridiagonal system of equations needs to be solved. The possible CPU, GPU implementations along with novel FPGA solutions with HLS (High Level Synthesis) will be shown. Performance is also analyzed and remarks on efficiency are made.
Keywords :
field programmable gate arrays; high level synthesis; instruction sets; multiprocessing systems; parallel architectures; Black-Scholes PDE; FPGA architecture; HLS; ISA; MIC; high level synthesis; instruction set architecture; many integrated core; many-core GPU; multicore CPU; parallel computer microarchitectures; parallel processor architectures; thread management; time-marching algorithms; Bandwidth; Computer architecture; Field programmable gate arrays; Graphics processing units; Pipeline processing; Pricing; Sockets;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7169062
Filename :
7169062
Link To Document :
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