DocumentCode
3322250
Title
A single Op-Amp 0+2 sigma-delta modulator
Author
Yao Liu ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution
Dept. of Electr., Univ. of Pavia, Pavia, Italy
fYear
2015
fDate
24-27 May 2015
Firstpage
2029
Lastpage
2032
Abstract
This paper describes a single op-amp 0+2 ΣΔ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ΣΔ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolution of the modulator and reduces the output swing of the op-amp. The mismatch of the multi-level DACs can be compensated for with DEM while the mismatch between the two stages can be canceled in the digital domain. Simulation results, carried out at the transistor level with a 0.18-μm CMOS technology, verify the effectiveness of the proposed architecture. The simulated FoM is 104 fJ/conv-step.
Keywords
CMOS integrated circuits; direct digital synthesis; operational amplifiers; quantisation (signal); sigma-delta modulation; transfer functions; ΣΔ architecture; CMOS technology; MASH techniques; bandwidth 2 MHz; digital domain; direct synthesis; multibit quantization; multilevel DAC; noise transfer function; op-amp reduction; sigma-delta modulator; single op-amp; size 0.18 mum; transistor level; word length 12 bit; Bandwidth; Clocks; Gain; Modulation; Multi-stage noise shaping; Quantization (signal); Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7169075
Filename
7169075
Link To Document