MOS transistor mismatch modelling for high voltage CMOS processes

Author

Posch, Werner ; Rappitsch, Gerhard ; Leonardelli, Georg

Author_Institution

Process Characterisation, Austriamicrosystems AG

fYear

2005

fDate

11-12 April 2005

Firstpage

256

Lastpage

260

Abstract

An algorithm is presented to extract device mismatch parameters for high voltage transistors. The mismatch parameters are determined in two steps. The device mismatch for the threshold voltage, the gain factor and the mobility reduction are extracted from a sensitivity model in saturation, whereas the extraction of the drift-resistance mismatch is carried out based on a MOS transistor model in the ohmic region. The extracted parameters are implemented as part of circuit simulation libraries to be used for Monte Carlo simulation. Production control parameters enable the monitoring of device mismatch for high voltage transistors

Keywords

CMOS integrated circuits; MOSFET; Monte Carlo methods; integrated circuit manufacture; integrated circuit technology; power integrated circuits; MOS transistor mismatch modelling; Monte Carlo simulation; device mismatch parameters; drift-resistance mismatch; gain factor; high voltage CMOS processes; high voltage transistors; mobility reduction; ohmic region; production control parameters; sensitivity model; threshold voltage; CMOS process; Circuit simulation; Current measurement; Libraries; MOSFETs; Parameter extraction; Semiconductor device modeling; Statistical analysis; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI

Conference_Location

Munich

Print_ISBN

0-7803-8997-2

Type

conf

DOI

10.1109/ASMC.2005.1438805

Filename

1438805