1.1-V 200 MS/s 12-bit digitally calibrated pipeline ADC in 40 nm CMOS

This paper presents a 1.1-V 200 MS/s pipeline ADC with 70 dB signal-to-noise-plus-distortion ratio (SNDR) and 54 mW power consumption. This performance is enabled by employing low gain amplifiers in the first two pipelined stages and digitally calibrate the inter-stage gain errors in the background using split ADC technique. To calibrate multistage in split ADC, Slope Mismatch Averaging (SMA) is used with a programmable-residue in the first stage. A low voltage two stage amplifier is used with feedforward compensation in its main loop and the common mode feedback (CMFB) loop to decrease the power consumption. Implemented in 40 nm CMOS, the ADC achieves more than 11 ENOB in post-layout simulation results.