A decoupled access/execute processor for matrix algorithms: architecture and programming

The authors describe a processor for the execution of a class of matrix algorithms according to the multimesh graph (MMG) mapping method, which is suitable as the processing cell in an application-specific array. The processor uses the decoupled access-execute model of computation, so that it consists of two programmable units: a processing unit (PU) and an access unit (AU). The two programs synchronize their execution through queues. The instruction set includes single-instruction loops with no overhead, and block- loops with just one extra instruction. All storage modules are accessed as FIFO queues, without the need for addressing mechanisms. The efficiency of the resulting code is high: for a class of matrix algorithms frequently used in signal processing applications, about 90% of the instructions executed correspond to arithmetic operations