Title :
Performance analysis of CMOS ICs in total dose environments
Author :
Kaul, N. ; Bhuva, B.L. ; Kerns, S.E.
Author_Institution :
Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA
Abstract :
A switch-level simulator (PARA) has been developed which identifies the total dose failure modes in CMOS digital ICs. The approach used is highly cost-effective in terms of the computation involved. PARA identifies all the possible failure modes and the critical subcircuit responsible for the occurrence of the failure. The dose level at which the failure occurs can also be extracted. PARA takes as its input a file containing the circuit topological information in SPICE-like format. In addition, it requires the individual characteristics of the transistors as a function of total dose exposure. PARA is designed to maintain compatibility with existing CAD (computer-aided design) tools and hence can be integrated with them easily to assist in the design and testing of CMOS ICs operating in the total dose radiation environment. The algorithms used are described, and simulation results are presented. It is concluded that the results obtained prove the validity of PARA and its superiority to the existing simulation packages
Keywords :
CMOS integrated circuits; circuit analysis computing; failure analysis; integrated circuit testing; radiation effects; CMOS ICs; circuit topological information; simulation packages; switch-level simulator; total dose environments; total dose failure modes; transistor characteristics; Circuit simulation; Computational modeling; Degradation; Failure analysis; Leakage current; Performance analysis; Radiation effects; Semiconductor device modeling; Switches; Threshold voltage;
Conference_Titel :
Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE
Conference_Location :
Columbia, SC
DOI :
10.1109/SECON.1989.132547
