A superconductive RAM memory design

Author

Smith, Stuart H., Jr. ; Krad, Hasan

Author_Institution

New Orleans Univ., LA, USA

fYear

1989

fDate

9-12 Apr 1989

Firstpage

1050

Abstract

A brief survey of contemporary superconductive RAMs (random-access memories) is given. A 16×1 RAM circuit which stores information with superconductive loop-currents that link unique pairs of connecting conductors is explained, read/write operations are described, and ways to minimize potential problems are suggested. In this RAM design, information is read out nondestructively, and the bit capacity of a node-pair circuit, with equal A and B matrices, is ( n²)/4, where n is the total number of connecting conductors (nodes) joining the AB plane. The minimum number of decoded address lines required is 4×(b^0.25), where b is the total bit capacity of the system

Keywords

integrated memory circuits; random-access storage; superconducting memory circuits; 16 bit; bit capacity; connecting conductors; decoded address lines; node-pair circuit; read/write operations; superconductive RAM memory design; superconductive loop-currents; total bit capacity; unique pairs; Circuits; Conducting materials; Conductors; Humans; Interference; Joining processes; Random access memory; Read-write memory; Superconductivity; Type II superconductors;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE

Conference_Location

Columbia, SC

Type

conf

DOI

10.1109/SECON.1989.132569

Filename

132569