A fast square rooter combining algorithmic and lookup table techniques

It is noted that lookup table implementations of a square root are very inefficient in terms of hardware, while algorithmic techniques are inefficient in terms of speed. The author considers square-root implementations combining both techniques, which are a compromise between speed and complexity. The proposed technique speeds up the algorithmic implementation by using a PLA (programmable logic array) lookup table to determine both the MSBs (most significant bits) of the square root and the square of these bits. The square is subtracted form the original number to obtain a partial remainder, and the remaining square-root bits are determined algorithmically