FPGA implementation for a recursive least square algorithm

A recursive least square algorithm is implemented in this paper. Memory Nonlinearity of digital receiver is compensated by using a blind identification algorithm based on nonlinear model. A least-squared blind identification criterion to minimize all the energy of the nonlinearity in the receiver´s output signal is implemented under circumstances of not knowing the information of the receiver´s input signal. The orders and memory depths of the Volterra model are tested and updated automatically. A double-precision arbitrary-dimensional matrix inversion module is implemented in the requirement of the least-squared method. The digital post calibration processes in real-time. Experimental results on the actual nonlinear circuit illustrate the validity of the implemented technique.