"The new frontier for testing: nanometer technologies"

The onset of deep sub-micron (now currently alluded to as nanometer technology) is changing the way chips are being designed and manufactured. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality. Test is one part of this process that is getting significant attention. An area once classified as a "back end" process in the design flow is moving closer to the "front end". Design methodologies are incorporating test-related structures in the beginning of the design cycle. Manufacturability of the complex designs caused by the excess silicon available is a significant issue. With these nanometer technologies comes a number of issues which the SIA Roadmap refers to as Grand Challenges. These include >1 GHz cycle time, higher sensitivity to crosstalk, and tester costs. This paper will examine the challenges that face testing in this new frontier.