High-performance low-power digital linear interpolation filter

Author

El-Moursy, Magdy A. ; Abdellatif, Ahmed G.

Author_Institution

Electron. Dept., German Univ. in Cairo, Cairo

fYear

2007

fDate

29-31 Dec. 2007

Firstpage

57

Lastpage

60

Abstract

A new technique to implement digital interpolation filter is presented in this paper. The technique employs a sample calculation functional block which reduces the hardware required to realize the filter by orders of magnitude. The filter is realized with 80times160 mum² using 65 nm CMOS technology. Over Sampling Rate of up to 256 is achieved for 16-bit digital data sampled at 705,600 bps. The filter dissipates 77.68 mW when operating at frequency of 833.3 MHz.

Keywords

CMOS integrated circuits; digital filters; CMOS technology; bit rate 705600 bit/s; calculation functional block; digital data sampling; filter dissipates; frequency 833.3 MHz; high-performance digital linear interpolation filter; low-power digital linear interpolation filter; power 77.68 mW; size 65 nm; Digital filters; Digital signal processing; Discrete Fourier transforms; Finite impulse response filter; Hardware; Information filtering; Information filters; Interpolation; Low pass filters; Nonlinear filters; DAC; DSP; Delta-Sigma Modulators; Digital Low Pass Filters; Digital interpolation; FFT; FIR; Oversampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2007. ICM 2007. Internatonal Conference on

Conference_Location

Cairo

Print_ISBN

978-1-4244-1846-6

Electronic_ISBN

978-1-4244-1847-3

Type

conf

DOI

10.1109/ICM.2007.4497661

Filename

4497661