SOPC based Asynchronous Pipelined DCT with self test capability

Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower power consumption, design reuse without compromise in speed. In this paper, a new technique i.e., "SOPC based Asynchronous Pipelining Technique" (SOPC - System On Programmable Chip) is used for designing and implementing FPGA based Low- Power VLSI Systems. In this approach, the soft core processor available within the FPGA is used to generate various control signals to control the asynchronous data flow in addition to its regular work as processor. Importantly, NIOS processor is also used to validate the results by comparing the results with a known set of test vectors. This type of verification and validation of the digital systems using NIOS provides higher speed and doesn\´t require any external hook up wires and I/O cards. To verify the efficacy of the proposed approach, an 8 tap DCT using Winograd algorithm is implemented as External Logic to the NIOS processor. The intermittent data between asynchronous pipelined stages are latched by using multiplexer based latches. The completion of each stage is informed to the NIOS processor using interrupts. In turn, NIOS processor generates various control signals to pass the intermittent data stored in the multiplexer based latches. The designed system has been implemented in a STRATIX EP1S25F780C5 FPGA SOPC kit. The results are validated using the same NIOS processor. In the proposed system, storage of intermittent data is done with multiplexer based latches instead of pipelined registers. Hence this approach results in obtaining the speed of a pipelined DCT with comparably lower power consumption. This approach is also avoiding the need for global clock signals and their consequences like skew problems.