A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems

As energy-constrained systems continue to reduce their power consumption, Unding an optimal point of operation for the principle components in the energy budget becomes increasingly important. With energy dominant system components like communication circuits, it is important to consider both energy-per-bit and power in the context of the system´s use cases. In this paper, we propose optimization of chip-to-chip links considering both energy-per-cycle and energy-per-bit to find the optimal operating voltage and activity factor while minimizing wasted energy and power. A fabricated 130 nm chip was used to verify this finding and resulted in an energy-per-bit of 0.38 pj/bit and power of 1.24 nW.