Title :
Minimum jitter adaptive decision feedback equalizer for 4PAM serial links
Author :
Al-Taee, Alaa R. ; Fei Yuan ; Ye, Andy
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada
Abstract :
This paper presents a minimum jitter-based adaptive decision feedback equalizer (DFE) for 4PAM serial links. For each signal level, a dedicated sign-sign least-mean-square (SS-LMS) algorithm is employed to adjust corresponding DFE tap coefficient as per data rate and the characteristics of channels. The proposed adaptive DFE is embedded in a 2 Gbps serial link over a 12-inch FR4 channel implemented in an IBM 130 nm 1.2V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes.
Keywords :
CMOS analogue integrated circuits; decision feedback equalisers; integrated circuit design; integrated circuit modelling; jitter; least mean squares methods; pulse amplitude modulation; BSIM4 device models; Cadence Design Systems; DFE tap coefficient; FR4 channel; IBM CMOS technology; PAM serial links; SS-LMS algorithm; Spectre; adaptive DFE; bit rate 2 Gbit/s; minimum jitter adaptive decision feedback equalizer; pulse amplitude modulation; sign-sign least-mean-square algorithm; size 12 inch; size 130 nm; voltage 1.2 V; CMOS integrated circuits; Charge pumps; Decision feedback equalizers; Engines; Jitter; Threshold voltage; Serial links; decision feedback equalization (DFE); inter-symbol interference (ISI); sign-sign least-mean-square (SS-LMS);
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7169285
