Non-intrusive testing of high-speed CML circuits

Author

Devdas, Vikram ; Ivanov, André

Author_Institution

Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada

fYear

1998

fDate

2-4 Dec 1998

Firstpage

172

Lastpage

178

Abstract

A new methodology for production phase testing of catastrophic short and open faults in Current Mode Logic (CML) circuits is proposed. The catastrophic faults induced in differential input CML circuits due to manufacturing defects are detected by manipulating the voltage levels of the inputs. The non-intrusive tests include functional (at-speed) tests, I_dd test, and a new test called common-mode test (CMT). Two high-speed interface circuits, a 622 Mbps SONET SIPO (Serial-in-Parallel-Out) and a PISO (Parallel-In-Serial-Out) are used as examples to illustrate the effectiveness of the tests. Using all three tests, SPICE simulations show that 88-90% fault coverage of catastrophic faults can be detected

Keywords

bipolar logic circuits; current-mode logic; fault location; high-speed integrated circuits; integrated circuit testing; logic testing; production testing; I_dd test; PISO; SONET SIPO; at-speed tests; catastrophic open faults; catastrophic short faults; common-mode test; current mode logic circuits; differential input CML circuits; fault coverage; functional tests; high-speed CML circuits; high-speed interface circuits; manufacturing defects; nonintrusive testing; production phase testing; voltage levels; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Manufacturing; Production; SONET; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

ISSN

1081-7735

Print_ISBN

0-8186-8277-9

Type

conf

DOI

10.1109/ATS.1998.741610

Filename

741610