An optimal time expansion model based on combinational ATPG for RT level circuits

Author

Inoue, Tomoo ; Hosokawa, Toshinori ; Mihara, Takahiro ; Fujiwara, Hideo

Author_Institution

Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan

fYear

1998

fDate

2-4 Dec 1998

Firstpage

190

Lastpage

197

Abstract

We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency

Keywords

automatic test pattern generation; design for testability; fault diagnosis; logic testing; sequential circuits; RT level circuits; acyclic sequential circuits; combinational ATPG; fault efficiency; hardware overhead; optimal time expansion model; partial scan designed register-transfer circuits; test generation; test length; time expansion models; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Design for testability; Hardware; Kernel; Logic; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

ISSN

1081-7735

Print_ISBN

0-8186-8277-9

Type

conf

DOI

10.1109/ATS.1998.741613

Filename

741613

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=332605