On-line error detection schemes for a systolic finite-field inverter

Author

Chuang, Yu-Chun ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

1998

fDate

2-4 Dec 1998

Firstpage

301

Lastpage

305

Abstract

Galois-field (GF) is a number system with a finite set of elements. It is widely used in error-control coding, cryptography, etc. Among its important arithmetic operations, inversion and division have been identified as the most complicated. In this paper, concurrent error detection (CED) schemes have been presented for a systolic GF(2^m) inverter that we have proposed recently. The CED circuitry tests the inverter concurrently while it is in normal operation to increase the reliability of the inverter. There is negligible performance penalty. Analysis shows that all single cell faults can be detected concurrently. The area overhead is less than 5% for 11 bits or longer words

Keywords

Galois fields; automatic testing; digital arithmetic; error detection; logic testing; systolic arrays; Galois-field; arithmetic operation; concurrent error detection schemes; inverter reliability; online error detection schemes; single cell faults; systolic GF(2^m) inverter; systolic finite-field inverter; Arithmetic; Automatic testing; Circuit faults; Circuit testing; Cryptography; Electrical fault detection; Fault detection; Galois fields; Inverters; Polynomials; System testing; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

ISSN

1081-7735

Print_ISBN

0-8186-8277-9

Type

conf

DOI

10.1109/ATS.1998.741629

Filename

741629