Noise tunable clock delayed domino logic using latched keeper

In this work, domino logic with a latched keeper technique is proposed. The circuit, which is used to implement the technique, utilizes a latch with standard domino. By using the simple structure, we can obtain better performance, noise immunity, and lower power consumption. The simulation results for a 65 nm CMOS technology show an improvement between 5% and 55.7% in delay and 8% and 15% in power consumption, over its previous suggestions.