• DocumentCode
    3326429
  • Title

    A new vision system: programmable logic devices and digital signal processor architecture (PLD+DSP)

  • Author

    Lorenzo, S. ; Mohamed, M.S.

  • fYear
    1991
  • fDate
    28 Oct-1 Nov 1991
  • Firstpage
    2014
  • Abstract
    The authors show a way to establish a good structure for an image processing system. Image processing algorithms are classified as a function of the input/output information structure. Then a whole system is created, with different processing architectures inside, one for each group in the classification. The main devices in the whole machine are a digital signal processor (DSP), and specific hardware designs into erasable programmable logic devices (EPLDs). It is shown how these specific designs can be made with a few different printed circuit boards, and specific circuits are loaded from a library into EPLD chips. This library is prepared in the computer, and the machine is easily adapted to a specific application
  • Keywords
    computer vision; digital signal processing chips; image processing; logic arrays; parallel architectures; pipeline processing; DSP; EPLD chips; computer vision; digital signal processor architecture; erasable programmable logic devices; image processing algorithm; parallel architectures; Digital signal processing chips; Digital signal processors; Hardware; Image processing; Machine vision; Printed circuits; Programmable logic devices; Signal design; Signal processing algorithms; Software libraries;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics, Control and Instrumentation, 1991. Proceedings. IECON '91., 1991 International Conference on
  • Conference_Location
    Kobe
  • Print_ISBN
    0-87942-688-8
  • Type

    conf

  • DOI
    10.1109/IECON.1991.239032
  • Filename
    239032