A 40 Gb/s packet switching architecture with fine-grained priorities

We discuss a novel architecture for very high speed packet switching with priority-based conflict resolution. An input-queued switch with N² queues is used to prevent head-of-line blocking. Unlike previous designs which use multiple FIFO queues to provide several priority levels, we use hardware priority queues with 16-bit priority encoding. To reduce the hardware complexity, we introduce the concept of grouping fixed-size packets into “ensembles” that are stored by reference in the priority queues. This approach yields large buffer capacity while using relatively short queues