DocumentCode
3326808
Title
A new high-speed burst transfer architecture DBTN: dynamic burst transfer time-slot-base network
Author
Shiomoto, Kohei ; Yamanaka, Naoaki
Author_Institution
NTT Network Service Syst. Labs., Musashino, Japan
fYear
1999
fDate
1999
Firstpage
161
Lastpage
166
Abstract
This paper proposes a new high-speed network architecture DBTN (dynamic burst transfer time-slot-base network), which is based on circuit-switched network technology. A routing tag is attached to a burst at an ingress edge node and the burst is self-routed in a DBTN network by creating a circuit dynamically. The routing tag, which is called time-slots-relay, is a series of link identifiers to the destination. The time-slots-relay consists of link identifiers from the ingress to the egress nodes and is used to create the circuit. Subsequent data is switched over the circuit being created in an on-the-fly fashion. A link identifier in the time-slots-relay is unique within each node. Each link identifier is loaded into address control memory (ACM) of each circuit-switched transit node, and the circuit to the destination is established. Subsequent user data follows immediately after the time-slots-relay and is sent over the established circuit. Thus short-lived fairly large data transfers like WWW traffic are efficiently carried. A circuit between adjacent nodes is created and released dynamically so bandwidth efficiency is improved compared with conventional circuit-switched networks. Time division multiplexing of the circuit-switched network is utilized so there is no delay jitter or loss. We address the performance of DBTN switches and report on the implementation of the system
Keywords
Internet; circuit switching; data communication; information resources; telecommunication control; telecommunication network routing; telecommunication traffic; DBTN; WWW traffic; address control memory; bandwidth efficiency; circuit-switched network; data transfers; dynamic burst transfer time-slot-base network; edge node; high-speed burst transfer architecture; link identifiers; performance; routing tag; self-routing; time division multiplexing; time-slots-relay; Bandwidth; Communication system traffic control; Delay effects; High-speed networks; Jitter; Routing; Switches; Switching circuits; Time division multiplexing; World Wide Web;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Communications and Networks, 1999. Proceedings. Eight International Conference on
Conference_Location
Boston, MA
ISSN
1095-2055
Print_ISBN
0-7803-5794-9
Type
conf
DOI
10.1109/ICCCN.1999.805511
Filename
805511
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