A 2.5-3.125Gbps clock and data recovery circuit for multi-standard transceivers

This paper describes the design of a 2.5 to 3.2 Gbps clock and data recovery circuit using a second-order analog phase interpolator. The jitter transfer characteristics of the circuit meets jitter tolerance specification that allows the design to operate for multi-standards. The CDR circuit operates from 2.5 to 3.2 Gbps and achieves a 40 psec(pp) jitter, 60 nsec settling time; with a ±5000 ppm offset frequency deviation. The designed circuits have a low power consumption of 14.4 mW at a 1.2 V supply. The CDR circuit was implemented in a generic 0.13 μm CMOS digital process with an area of only 0.01 mm².