DocumentCode :
3326818
Title :
Jigsaw: scalable software-defined caches
Author :
Navada, Sandeep ; Choudhary, Niket K. ; Wadhavkar, Salil V. ; Rotenberg, Eric
Author_Institution :
CPU Design Center, Qualcomm, Raleigh, NC, USA
fYear :
2013
fDate :
7-11 Sept. 2013
Firstpage :
213
Lastpage :
224
Abstract :
A single-ISA heterogeneous chip multiprocessor (HCMP) is an attractive substrate to improve single-thread performance and energy efficiency in the dark silicon era. We consider HCMPs comprised of non-monotonic core types where each core type is performance-optimized to different instruction-level behavior and hence cannot be ranked - different program phases achieve their highest performance on different cores. Although non-monotonic heterogeneous designs offer higher performance potential than either monotonic heterogeneous designs or homogeneous designs, steering applications to the best-performing core is challenging due to performance ambiguity of core types.
Keywords :
microprocessor chips; multiprocessing systems; HCMP; application steering; best performing core; dark silicon era; energy efficiency; heterogeneous chip multiprocessors; instruction level behavior; nonmonotonic core selection; nonmonotonic core types; nonmonotonic heterogeneous designs; single ISA heterogeneous chip multiprocessor; single thread performance; Algorithm design and analysis; Clocks; Genetic algorithms; Microarchitecture; Multicore processing; Pipelines; Radiation detectors; NUCA; cache; isolation; memory; partitioning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on
Conference_Location :
Edinburgh
ISSN :
1089-795X
Print_ISBN :
978-1-4799-1018-2
Type :
conf
DOI :
10.1109/PACT.2013.6618811
Filename :
6618811
Link To Document :
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