A novel All Digital Delay Lock Loop (ADDLL)

The use of delay locked loops (DLL) for clock recovery is currently receiving an increased interest. In this work a novel all digital DLL (ADDLL) circuit for data recovery is presented. The design is based on dividing the DLL circuit into independent groups of taps for optimum tap selection. A controller circuit is added to control tap switching. The ADDLL architecture is applied, as an example, to the problem of USB 2.0 clock recovery. The proposed ADDLL-based USB 2.0 clock recovery circuit is implemented down to the logic level using the AMS 0.35 mum CMOS technology. The proposed ADDLL is subjected to an input signal jitter and simulated under typical and worst case conditions. Simulation results show that the performance of the proposed circuit meets the requirements of USB 2.0 clock recovery.