DocumentCode
332704
Title
Technology mapping for domino logic
Author
Min Zhao ; Sapatnekar, S.S.
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
1998
fDate
8-12 Nov. 1998
Firstpage
248
Lastpage
251
Abstract
Domino logic is a popular configuration for implementing high-speed circuits. An algorithm for domino logic mapping, under a parameterized library style, is presented. Practical design methods, such as the use of multi-output domino and wide domino gates, are incorporated within the technology mapping framework. The technique can handle large circuits with small computational overheads, and shows improvements of up to about 37% over existing methods.
Keywords
libraries; logic CAD; logic gates; domino logic; domino logic mapping algorithm; high-speed circuits; multi-output domino gates; parameterized library style; small computational overheads; technology mapping; wide domino gates; Computer networks; Concurrent computing; Cost function; Design methodology; Dynamic programming; Libraries; Logic circuits; Permission; Tree graphs; Vegetation mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
1-58113-008-2
Type
conf
DOI
10.1109/ICCAD.1998.144274
Filename
742880
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