DocumentCode :
3327062
Title :
Optimizing second generation current conveyors using particle swarm optimization
Author :
Cooren, Yann ; Fakhfakh, Mourad ; Loulou, Mourad ; Siarry, Patrick
Author_Institution :
LISSI, Univ. of Paris XII, Creteil
fYear :
2007
fDate :
29-31 Dec. 2007
Firstpage :
365
Lastpage :
368
Abstract :
This brief paper deals with using the particle swarm optimization metaheuristic for optimally sizing CMOS positive second generation current conveyors (CCII+). Both static and dynamic performances are improved. Pareto front is generated while minimizing parasitic X-port input resistance RX and maximizing current high cut off frequency fci. The translinear implementation in CMOS technology is presented. Boundaries of the generated Pareto boarder are 400 Omega and 2 GHz for RX and fci respectively. SPICE simulation results are presented to validate obtained sizing.
Keywords :
CMOS integrated circuits; Pareto optimisation; SPICE; UHF circuits; particle swarm optimisation; Pareto front; SPICE simulation; frequency 2 GHz; optimally sizing CMOS technology; parasitic X-port input resistance; particle swarm optimization metaheuristics; resistance 400 ohm; second generation current conveyor optimization; translinear implementation; CMOS technology; Character generation; Circuits; Frequency; Impedance; Laboratories; Particle swarm optimization; SPICE; Space technology; Voltage; CMOS; Particle Swarm Optimization; translinear CCII+;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2007. ICM 2007. Internatonal Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-1846-6
Electronic_ISBN :
978-1-4244-1847-3
Type :
conf
DOI :
10.1109/ICM.2007.4497730
Filename :
4497730
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3327062
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