Title :
A linear optimal test generation algorithm for interconnect testing
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
A linear optimal test generation algorithm is proposed to decompose serial test vectors into segments with one for each driver. Each driver is assigned a serial vector with two or more transitions for the detection of net and driver faults. As compared to the conventional counting and transition sequences, the reduction is up to 20% for buses and 36% for general networks.
Keywords :
automatic test pattern generation; boundary scan testing; fault location; integrated circuit interconnections; integrated circuit testing; buses; driver fault detection; general networks; interconnect testing; linear optimal test generation algorithm; net fault detection; segments; serial test vector decomposition; Circuit faults; Circuit testing; Costs; Design for testability; Fault detection; Integrated circuit interconnections; Permission; Sockets; TV; Vectors;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144280
