A fast single slope ADC with vernier delay line technique

Author

Lin, W.F. ; Chou, H.P.

Author_Institution

Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2009

fDate

Oct. 24 2009-Nov. 1 2009

Firstpage

313

Lastpage

317

Abstract

The paper presents a 9-bit single slope analog to digital converter (ADC) using a two-level vernier delay line (VDL) technique. The amplitude to time conversion architecture is aim to reduce the errors due to comparator delays and input offset. Results indicated that the comparator timing error has been reduced to less than 10 ps and the offset voltage is less than 1%. The time conversion part has the maximum sampling rate of 50Msps and the time resolution of 19.5ps with the differential non-linearity (DNL) within Â±0.5 LSB, and the integral non-linearity (INL) within -0.22 and 0.56 LSB. The ADC has a sampling rate of 5 Msps and is realized with the CMOS 0.18um 1P6M technology.

Keywords

analogue-digital conversion; comparators (circuits); nuclear electronics; 9-bit single slope analog-digital converter; CMOS 1P6M technology; amplitude-to-time conversion architecture; comparator delays; comparator timing error; differential nonlinearity; input offset; integral nonlinearity; offset voltage; sampling rate; single slope ADC; time resolution; two-level vernier delay line technique; CMOS technology; Clocks; Delay effects; Delay lines; Radiation detectors; Sampling methods; Time measurement; Timing; Virtual manufacturing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE

Conference_Location

Orlando, FL

ISSN

1095-7863

Print_ISBN

978-1-4244-3961-4

Electronic_ISBN

1095-7863

Type

conf

DOI

10.1109/NSSMIC.2009.5401729

Filename

5401729