• DocumentCode
    332714
  • Title

    Using precomputation in architecture and logic resynthesis

  • Author

    Hassoun, S. ; Ebeling, C.

  • Author_Institution
    Tufts Univ., Medford, MA, USA
  • fYear
    1998
  • fDate
    8-12 Nov. 1998
  • Firstpage
    316
  • Lastpage
    323
  • Abstract
    Although tremendous advances have been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by clever designers. This, in part, is a result of logic synthesis not optimizing across register boundaries. We focus on precomputation as a resynthesis technique capable of resynthesizing across register boundaries. By using precomputation, a critical signal is computed earlier in time, thus allowing it to be combinationally optimized with logic from previous pipeline stages. Precomputation automatically discovers some standard circuit transformations like bypassing and lookahead. In addition, precomputation can be used in conjunction with combinational logic synthesis to resynthesize a circuit to obtain better performance. The paper contributes to the understanding and development of precomputation. First, it provides a synthesis algorithm for precomputation. Second, it demonstrates how precomputation can be used to improve sequential logic resynthesis and reports the results of applying a heuristic to a subset of the MCNC benchmarks. Third, it illustrates how precomputation generalizes and unifies bypassing and lookahead-two important and practical architectural transformations often used in processor design and high level synthesis of DSP processors. Finally, it clarifies the relationships among precomputation, retiming, and implicit retiming.
  • Keywords
    combinational circuits; heuristic programming; high level synthesis; sequential circuits; DSP processors; architecture resynthesis; combinational logic synthesis; implicit retiming; logic resynthesis; pipeline stages; precomputation; register boundaries; sequential logic resynthesis; standard circuit transformations; synthesis algorithm; Circuit synthesis; Clocks; Delay; High level synthesis; Logic circuits; Logic design; Pipelines; Process design; Registers; Signal synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    1-58113-008-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1998.144285
  • Filename
    742891