DocumentCode
3327180
Title
A new method for power estimation and optimization of combinational circuits
Author
Aldeen, Ahmed ; Al-Asaad, Hussain
Author_Institution
Intel Corp., Folsom, CA
fYear
2007
fDate
29-31 Dec. 2007
Firstpage
395
Lastpage
398
Abstract
One of the challenges of low power methodologies for digital systems is saving power consumption in these systems without compromising performance. In this paper we propose a new method for estimating dynamic power consumption in combinational circuits. The method enables us to optimize the power consumption of typical combinational circuits.
Keywords
circuit optimisation; combinational circuits; low-power electronics; combinational circuits; digital systems; dynamic power estimation; optimization; CMOS technology; Capacitance; Combinational circuits; Digital circuits; Energy consumption; Equations; Logic circuits; Optimization methods; Switching circuits; Voltage; Power estimation; combinational circuits; low-power design; power optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2007. ICM 2007. Internatonal Conference on
Conference_Location
Cairo
Print_ISBN
978-1-4244-1846-6
Electronic_ISBN
978-1-4244-1847-3
Type
conf
DOI
10.1109/ICM.2007.4497737
Filename
4497737
Link To Document