DocumentCode :
3327309
Title :
Task sampling: Computer architecture simulation in the many-core era
Author :
Grass, Thomas
Author_Institution :
Barcelona Supercomput. Center, Univ. Politec. de Catalunya, Barcelona, Spain
fYear :
2013
fDate :
7-11 Sept. 2013
Firstpage :
405
Lastpage :
405
Abstract :
Chip Multi-Processors (CMPs) are evolving towards ever increasing core counts. Task-based programming models are a promising candidate for exploiting the parallelism offered by these machines. Simulation, the prevailing design methodology in computer architecture, is prohibitively time consuming, when it comes to CMPs featuring 1000s of cores. Sampled simulation is a standard technique for reducing simulation time for single-threaded architectures. Recently, these techniques have been extended to allow for simulation of multi-threaded systems. However, they have not been assessed for dynamically scheduled multi-threaded programs. In this work we use the OmpSs programming model [4]. OmpSs, an extension of OpenMP, allows to declare code blocks as tasks and to specify data consumed and produced by each task. The runtime environment executes tasks, potentially out of program order, on available cores, similar to the out-oforder execution in a superscalar processor.
Keywords :
computer architecture; multi-threading; multiprocessing systems; CMP; OmpSs programming model; OpenMP; chip multiprocessors; code block; computer architecture; many-core era; multithreaded system; single-threaded architecture; superscalar processor; task sampling; task-based programming model; Accuracy; Analytical models; Benchmark testing; Computational modeling; Computer architecture; Electronic mail; Programming;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on
Conference_Location :
Edinburgh
ISSN :
1089-795X
Print_ISBN :
978-1-4799-1018-2
Type :
conf
DOI :
10.1109/PACT.2013.6618838
Filename :
6618838
Link To Document :
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