Iterative decoding of orthogonally concatenated code for fiber communications

This paper presents a 10Gb/s concatenated BCH iterative decoder of super FEC. This iterative decoder consists of 3 row decoding modules and 2 column decoding modules which are cascaded together. Parallel decoding strategy is employed in the row decoder which reduces the total decoding latency from 1928 cycles to 578 cycles. Taking advantage of RAM blocks, the implementation of column decoding becomes easier compared to original structure. Other techniques like multiplexing and pipeline technology are adopted to improve the path delay and resource consumption. A 10Gb/s implementation is realized on FPGA device under the working frequency of 156.25 MHz.