Title :
A dual symbol arithmetic coder architecture with reduced memory for JPEG2000
Author :
Liu, Kai ; Li, Yunsong
Author_Institution :
Sch. of Comput. Sci. & Technol., Xidian Univ., Xi´´an, China
Abstract :
A dual-symbol arithmetic coder architecture with reduced memory is presented for JPEG2000. Eight process elements are used for the prediction of probability interval A. And the use of a dedicated Probability Estimation Table decreases the internal memory greatly. Upon FPGA synthesis results, the architecture´s throughput can reach 96.60M context symbols per second with an internal memory size of 1509 bits.
Keywords :
computer architecture; digital arithmetic; field programmable gate arrays; image coding; probability; FPGA synthesis; JPEG2000; dual symbol arithmetic coder architecture; memory size; probability estimation table; probability interval; reduced memory; storage capacity 1509 bit; Clocks; Computer architecture; Context; Field programmable gate arrays; Indexes; Registers; Transform coding; Architecture; Arithmetic Coder; Image Compression;
Conference_Titel :
Image Processing (ICIP), 2010 17th IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-7992-4
Electronic_ISBN :
1522-4880
DOI :
10.1109/ICIP.2010.5651117
