DocumentCode
332738
Title
Power invariant vector sequence compaction
Author
Pinar, A. ; Liu, C.L.
Author_Institution
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
fYear
1998
fDate
8-12 Nov. 1998
Firstpage
473
Lastpage
476
Abstract
Simulation-based power estimation is commonly used for its high accuracy, despite excessive computation times. Techniques have been proposed to speed it up by transforming a given sequence into a shorter one while preserving the power consumption characteristics of the original sequence. This work proposes a novel method to compact a given input vector sequence to improve on the existing techniques. We propose a graph model to transform the problem to the problem of finding a heaviest weighted trail in a directed graph. We also propose a heuristic based on min-cost flow algorithms, using the graph model. Furthermore, we show that generating multiple input sequences yields better solutions in terms of both accuracy and simulation time. Experiments showed that significant reduction in simulation times can be achieved with extremely accurate results. Experiments also showed that the generation of multiple sequences improved the results further both in terms of accuracy and simulation time.
Keywords
SPICE; circuit CAD; circuit simulation; digital simulation; directed graphs; heuristic programming; CAD; SPICE; computation times; directed graph; experiments; graph model; heaviest weighted trail; heuristic; min-cost flow algorithms; power consumption; power invariant vector sequence compaction; simulation-based power estimation; Circuit simulation; Combinational circuits; Compaction; Computer science; Design optimization; Energy consumption; Frequency estimation; Permission; Power dissipation; Power generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
1-58113-008-2
Type
conf
DOI
10.1109/ICCAD.1998.144310
Filename
742951
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