Title :
Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology
Author :
Qi Wang ; Vrudhula, S.B.K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
We address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V/sub T/ technology. A novel and efficient heuristic alogrithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.
Keywords :
CMOS logic circuits; circuit optimisation; logic CAD; CMOS digital circuits; MCNC91 benchmark circuits; circuit graph enumeration; deep submicron CMOS circuits; delay constrained minimization; dual V/sub T/ technology; heuristic alogrithm; leakage power; power reduction; static power optimization; CMOS technology; Capacitance; Circuits; Delay; Energy consumption; Geometry; Permission; Power dissipation; Switches; Threshold voltage;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144313
