Title :
Robust latch mapping for combinational equivalence checking
Author :
Burch, J.R. ; Singhal, V.
Author_Institution :
Cadence Berkeley Labs., USA
Abstract :
Existing literature on combinational equivalence checking concentrates on comparing combinational blocks and assumes that a latch mapping (register mapping) has already been constructed. We describe an algorithm for automatically constructing a latch mapping. It is based on the functionality of the circuits being compared rather than on heuristics. As a result, if two circuits are combinationally equivalent, then our algorithm is guaranteed to find a latch mapping. Our empirical results show that the method is practical on large circuits.
Keywords :
equivalence classes; formal verification; logic CAD; circuit functionality; combinational blocks; combinational equivalence checking; large circuits; register mapping; robust latch mapping; Circuit synthesis; Computer bugs; Debugging; Latches; Permission; Registers; Robustness; Sequential circuits; Signal design; Signal mapping;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144324