Title :
Optimized Message Passing Schedules for LDPC Decoding
Author :
Radosavljevic, Predrag ; De Baynast, Alexandre ; Cavallaro, Joseph R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX
fDate :
Oct. 28 2005-Nov. 1 2005
Abstract :
The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a `turbo-scheduling´ applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that `turbo-scheduling´ applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the check-node messages (columns of the parity check matrix); and 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedules
Keywords :
message passing; parity check codes; scheduling; turbo codes; LDPC decoding; belief propagation algorithm; check-node messages; frame error rate; optimized message passing schedules; parity check matrix; turbo-codes; turbo-scheduling; Acceleration; Algorithm design and analysis; Belief propagation; Convergence; Error analysis; Iterative decoding; Message passing; Parity check codes; Scheduling algorithm; Turbo codes;
Conference_Titel :
Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0131-3
DOI :
10.1109/ACSSC.2005.1599818