A survey of gallium arsenide technology and fault characterization in basic gates

Author

Al-Arian, Sami A. ; Abujbara, Hussam Y.

Author_Institution

Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA

fYear

1989

fDate

9-12 Apr 1989

Firstpage

1156

Abstract

GaAs technology is reviewed from a testing-engineer point of view, and the fault behavior of GaAs transistor is examined. Timing faults are shown to be the most serious faults in GaAs. Timing algebra is presented to propagate and detect timing faults in the gate-level simulation. Simulation results for the same type of faults in a DCFL (direct-coupled FET logic) inverter are shown using the modified SPICE3 MESFET model and they were compared with the corresponding results for high-electron-mobility transistor simulation model. Standards for fault behavior study are listed to assist in drawing useful comparisons among different GaAs technologies. Finally, it is suggested that it might be possible to make use of existing CMOS fault models to detect both timing and traditional stuck-at faults in GaAs

Keywords

III-V semiconductors; Schottky gate field effect transistors; fault location; field effect integrated circuits; gallium arsenide; high electron mobility transistors; integrated circuit testing; integrated logic circuits; logic testing; reviews; CMOS fault models; DCFL invertor; GaAs technology; HEMT simulation model; IC testing; III-V semiconductors; direct-coupled FET logic; fault characterization; gate-level simulation; high-electron-mobility transistor; logic testing; modified SPICE3 MESFET model; stuck-at faults; timing algebra; timing faults; Algebra; FETs; Fault detection; Gallium arsenide; HEMTs; MESFETs; Pulse inverters; Semiconductor device modeling; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE

Conference_Location

Columbia, SC

Type

conf

DOI

10.1109/SECON.1989.132605

Filename

132605