Title :
The drastic changes in the electrical properties of doped hydrogenated amorphous silicon as a resistive layer material during vacuum packaging processes in field emission display
Author :
Ha, J.K. ; Chung, B.H. ; Han, S.Y. ; Choi, J.O. ; Kim, H.G.
Author_Institution :
Flat Panel Display Lab., Ajou Univ., Suwon, South Korea
Abstract :
Summary form only given. The integration of a resistive layer into the field emitter array has been a gigantic step in bringing such an emitter array into the area of electron sources used in displays (Ghis et al, 1991; Levine, 1996; baptist et al, 1997). When the resistive layer is integrated into an FED, the vacuum packaging process, where the face plate and base plate are aligned and sealed together to evacuate the inner volume, is of utmost concern due to the high process temperature. The field emission characteristics of a 10×10 FEA with 1% PH3 doped a-Si:H as resistive layer were measured both before and after annealing at 470°C for 30 min in Ar ambient. The gate voltage for emission current of 10 nA per tip increased from 70 V to 93 V. Together with the fact that there is little change in field emission characteristics of FEA without resistive layer during the vacuum packaging process (Jung et al, 1999), the drastic change in current-voltage behavior of the resistive layer suggests that a change in emission characteristics during vacuum packaging process may be caused by an increase in a-Si:H resistivity
Keywords :
amorphous semiconductors; annealing; electric current; electrical resistivity; elemental semiconductors; field emission displays; hydrogen; packaging; seals (stoppers); semiconductor thin films; silicon; vacuum techniques; 10 nA; 10 pixel; 100 pixel; 30 min; 470 C; 70 to 93 V; Ar annealing ambient; FEA; FED; PH3; PH3 doped a-Si:H resistive layer; Si:H; a-Si:H resistivity; annealing; base plate; current-voltage behavior; doped hydrogenated amorphous silicon resistive layer; electrical properties; electron source; emission characteristics; emission current; face plate; field emission characteristics; field emission display; field emitter array; gate voltage; plate alignment; plate sealing; process temperature; resistive layer integration; vacuum packaging processes; Amorphous silicon; Annealing; Conductivity; Field emitter arrays; Flat panel displays; Glass; Hydrogen; Packaging; Resists; Voltage;
Conference_Titel :
Vacuum Microelectronics Conference, 2001. IVMC 2001. Proceedings of the 14th International
Conference_Location :
Davis, CA
Print_ISBN :
0-7803-7197-6
DOI :
10.1109/IVMC.2001.939731