Title :
Design and Implementation of LDPC Codes for DVB-S2
Author :
Yadav, Manoj K. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., MN
fDate :
Oct. 28 2005-Nov. 1 2005
Abstract :
In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA
Keywords :
digital video broadcasting; matrix algebra; parity check codes; DVB-S2; LDPC codes; Xilinx Virtex-II XC2V8000 FPGA; Bipartite graph; Block codes; Cities and towns; Code standards; Decoding; Digital video broadcasting; Field programmable gate arrays; Forward error correction; Parity check codes; Sparse matrices;
Conference_Titel :
Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0131-3
DOI :
10.1109/ACSSC.2005.1599847
