DocumentCode
332821
Title
A layout-based approach for ordering scan chain flip-flops
Author
Makar, Samy
Author_Institution
Cirrus Logic Inc., Fremont, CA, USA
fYear
1998
fDate
18-23 Oct 1998
Firstpage
341
Lastpage
347
Abstract
A new practical layout-based approach for ordering flip-flop scan chains is presented. This approach can reduce the stitching wire length by an order of magnitude, and dramatically improve circuit routability
Keywords
automatic testing; combinational circuits; design for testability; flip-flops; large scale integration; logic testing; C++ language; LSI; circuit routability; combinational logic; flip-flop scan chains; hierarchical layout; layout; scan chain flip-flops; scan order; stitching wire length; Circuits; Costs; Flip-flops; High level synthesis; Iterative algorithms; Logic; Routing; Testing; Traveling salesman problems; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743172
Filename
743172
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