DocumentCode :
332827
Title :
Test generation in VLSI circuits for crosstalk noise
Author :
Chen, Weiyu ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1998
fDate :
18-23 Oct 1998
Firstpage :
641
Lastpage :
650
Abstract :
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects
Keywords :
CMOS integrated circuits; VLSI; automatic test pattern generation; combinational circuits; crosstalk; integrated circuit testing; integrated logic circuits; logic testing; waveform generators; PODEM-like static value; VLSI circuits; analog cost function; crosstalk noise; digital combinational circuits; dynamic signals; equivalent inverter; gate delay; inverter; logic error; logic gate; mixed-signal test generator; modeling; non-square wave pulse; output waveform; rise/fall times; signal arrival times; signal speedup; slowdown; timing information; two-vector tests; Circuit testing; Combinational circuits; Crosstalk; Delay; Pulse circuits; Pulse generation; Pulse inverters; Signal generators; Switching circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-5093-6
Type :
conf
DOI :
10.1109/TEST.1998.743208
Filename :
743208
Link To Document :
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