Parallel processing of finely grained tasks. Arbitrating synchronizer and parallel scheduler

A method of reducing overhead caused by the processor synchronization process and common memory access in finely grained tasks is described. The authors propose a hardware configuration to eliminate the synchronization time and a scheduler which minimizes the redundant accesses to shared memory. The proposed scheduler algorithm is processed in parallel. The processes share the common upper bound and the lower bound function which includes the preparation time for shared memory access. The effectiveness of the proposed scheme was confirmed by applying it to the computation of Newton-Euler equations for dynamic arm control, using a multiple digital signal processing system with four TMS320C25 processors