Title :
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers
Author :
Papameletis, Christos ; Keller, Brion ; Chickermane, Vivek ; Hamdioui, Said ; Marinissen, Erik Jan
Abstract :
This paper proposes a design-for-test architecture for efficient testing of 3-D ICs. The DfT architecture supports multiple dies, test data compression, and embedded cores. Commercial EDA tools are used to implement the DfT architecture.
Keywords :
data compression; design for testability; electronic design automation; integrated circuit testing; three-dimensional integrated circuits; 3D SIC; 3D integrated circuits; DfT architecture; commercial EDA tools; design-for-test architecture; embedded cores; multiple dies; multiple towers; test data compression; three-dimensional stacked integrated circuits; tool flow; Circuit synthesis; Integrated circuit interconnections; Poles and towers; System architecture; System-on-chip; Three dimensional displays;
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2015.2424422
