Title :
Minimized power consumption for scan-based BIST
Author :
Gerstendörfer, Stefan ; Wunderlich, Hans-Joachim
Author_Institution :
Lab. of Comput. Archit., Stuttgart Univ., Germany
Abstract :
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; fault simulation; integrated circuit testing; logic testing; power consumption; LFSR; STUMPS architecture; decoder synthesis; design modifications; digital system testing; fault coverage; fault simulation; gating logic; low power design; masking; minimized power consumption; multiple scan paths; random patterns suppression; scan path activity; scan-based BIST; shifting; synthesis of additional logic; Built-in self-test; Circuit testing; Costs; Counting circuits; Digital systems; Energy consumption; Logic design; Power dissipation; Power supplies; System testing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805616