DocumentCode :
3328614
Title :
CART: Communication-Aware Routing Technique for Application-Specific NoCs
Author :
Tornero, R. ; Ordua, J.M. ; Mejia, Andres ; Flich, J. ; Duato, J.
Author_Institution :
Univ. de Valencia, Valencia
fYear :
2008
fDate :
3-5 Sept. 2008
Firstpage :
26
Lastpage :
31
Abstract :
Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manufacturing defects or even real-time failures often make the resulting topology to become irregular, preventing the use of traditional routing algorithms. This scenario shows the need for topology-agnostic routing algorithms that provide a valid routing solution when applied over any topology. Moreover, in order to deal with run-time failures, the routing algorithm should be able to fit runtime constraints. This paper proposes a new communication-aware routing technique, referred to as CART, that optimizes the network performance for application-specific NoCs. CART combines a flexible, topology-agnostic routing algorithm with a communication-aware mapping technique that matches the traffic generated by the application with the available network bandwidth. Since the mapping technique can be pruned as needed in order to fit either quality function values or time constraints, CART can be adapted to fit with different computational costs. The evaluation results show that CART significatively improves network performance in terms of both latency and power consumption.
Keywords :
network routing; network topology; network-on-chip; CART; application-specific NoC; communication-aware mapping technique; communication-aware routing technique; complex on-chip communication problems; network-on-chip; power dissipation; topology-agnostic routing algorithms; two-dimensional meshes; Bandwidth; Delay; Manufacturing; Network topology; Network-on-a-chip; Power dissipation; Routing; Runtime; Telecommunication traffic; Time factors; Networks-on-Chip; Routing technique;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on
Conference_Location :
Parma
Print_ISBN :
978-0-7695-3277-6
Type :
conf
DOI :
10.1109/DSD.2008.19
Filename :
4669215
Link To Document :
بازگشت