Title :
Automatic timing margin failure location analysis by CycleStretch method
Author :
Matsumoto, Mitsuo ; Ikeda, Yoshiharu
Author_Institution :
ADVANTEST Corp., Tokyo, Japan
Abstract :
The CycleStretch principle and an application example were announced at ITC in 1994. However, the SOC (System on a Chip) developed in recent years generally has a built-in PLL, and therefore, adaptation of CycleStretch has been considered difficult. This paper proposes a method that allows the CycleStretch method to be applied to the SOC with a built-in PLL using conventional LSI test systems, and introduces an example of a CycleStretch application to an SOC with a built-in PLL
Keywords :
application specific integrated circuits; automatic test pattern generation; critical path analysis; fault location; integrated circuit testing; logic simulation; phase locked loops; timing; CycleStretch method; LSI test systems; SOC; System on Chip; automatic timing margin failure location analysis; built-in PLL; critical speed paths; logic simulation; Analytical models; Circuit simulation; Failure analysis; Large scale integration; Logic; Performance evaluation; Phase locked loops; System-on-a-chip; Testing; Timing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805637
