Title :
Delay testing of SOI circuits: Challenges with the history effect
Author :
MacDonald, Eric ; Touba, Nur A.
Author_Institution :
Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
Abstract :
Testing Partially-Depleted Silicon-On-Insulator (PD-SOI) integrated circuits presents new challenges that were not concerns in previous bulk CMOS technologies. Gates are affected by a variation in delay based on threshold voltage fluctuations. The fluctuations are dependent on the switching history of the device and this poses a serious challenge with regard to testing delays. To ensure worst-case operation, pre-conditioning of the path is necessary prior to a delay test. This paper provides background on SOI device operation and describes why and how pre-conditioning is accomplished. It is shown that a three-pattern delay test where the V1 and V3 patterns are the same is required to pre-condition the path for worst-case delay. Two novel scan latch designs that are capable of applying the three-pattern tests are presented
Keywords :
CMOS digital integrated circuits; automatic test pattern generation; critical path analysis; delay estimation; integrated circuit design; integrated circuit testing; low-power electronics; silicon-on-insulator; timing; ATPG; SOI CMOS circuits; V1 patterns; V3 patterns; delay testing; history effect; low power high performance digital circuits; partially-depleted SOI integrated circuits; path pre-conditioning; pulse stretching phenomenon; scan latch designs; switching history; three-pattern delay test; threshold voltage fluctuations; worst-case delay; worst-case operation; CMOS integrated circuits; CMOS technology; Circuit testing; Delay effects; Fluctuations; History; Integrated circuit technology; Integrated circuit testing; Silicon on insulator technology; Threshold voltage;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805640
