Title :
A DFT technique for high performance circuit testing
Author :
Shashaani, Mansour ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. In addition, various implementations aspects of this technique are addressed
Keywords :
CMOS digital integrated circuits; VLSI; design for testability; fault diagnosis; flip-flops; integrated circuit testing; timing; 6×6 multiplier; CMOS VLSI; DFT technique; controlled delay element; defect detection; high clock frequencies; high performance circuit testing; high performance integrated circuits; pulse triggered flip-flop; timing failures; Accuracy; Circuit testing; Clocks; Costs; Frequency; Integrated circuit testing; Manufacturing; Silicon compounds; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805641
